题解 | #根据状态转移表实现时序电路#三段式FSM

`timescale 1ns/1ns

module seq_circuit( input A , input clk , input rst_n,

  output   wire        Y   

); reg [1:0] state; reg [1:0] next_state; reg Y1; assign Y=Y1;

always @(*)begin
    Y1=&state;
end

always @(*)begin
    next_state[0]=~state[0];
    next_state[1]=(^(state))^A;
end

always@(posedge clk or negedge rst_n)begin
    if(~rst_n)begin
        state<=0;
    end
    else begin
        state<=next_state;
    end
end

endmodule