题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
    input                 clk         ,   
    input                 rst_n        ,
    input                valid_a        ,
    input                 data_a        ,
 
     output        reg    ready_a        ,
     output    reg            valid_b        ,
    output  reg [5:0]     data_b
);
    always @(posedge clk or negedge rst_n ) begin
       if(!rst_n)
              ready_a <= 'd0;
       else
              ready_a <= 1'd1;
    end

    reg [2:0] cnt;
    always@(posedge clk or negedge rst_n)
    if(!rst_n)
        cnt <= 0;
    else if(valid_a)begin
        if(cnt==3'd5)
            cnt <= 0;
        else
            cnt <= cnt + 1;
    end

    reg [5:0] data_parallel;
    always@(posedge clk or negedge rst_n)
    if(!rst_n)
        data_parallel <= 0;
    else if(valid_a)
        data_parallel[cnt] <= data_a;
    
    always@(posedge clk or negedge rst_n)
    if(!rst_n)begin
        valid_b <= 0;   
        data_b <= 0;     
    end
    else if(cnt == 5) begin
        data_b <= {data_a,data_parallel[4:0]};        
        valid_b <= 1;
    end
    else begin
        data_b <= data_b;
        valid_b <= 0;
    end



endmodule