题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

    parameter idle=3'd0, s0=3'd1, s1=3'd2, s2=3'd3, s3=3'd4;
    reg[2:0] c_state, n_state;
    
    always @(posedge clk or negedge rst_n)begin
        if(!rst_n)
            c_state<=idle;
        else
            c_state<=n_state;
    end
    
    always @(*)begin
        case(c_state)
            idle:    n_state=data_valid?(~data?s0:idle):idle;
            s0:    n_state=data_valid?(data?s1:s0):s0;
            s1:    n_state=data_valid?(data?s2:s0):s1;
            s2:    n_state=data_valid?(data?idle:s3):s2;
            s3:    n_state=data_valid?(data?s1:s0):idle;
            default:    n_state=idle;
        endcase
    end
    
    always @(posedge clk or negedge rst_n)begin
        if(!rst_n)
            match<=0;
        else if(n_state==s3)
            match<=1;
        else
            match<=0;
    end

        
      
    
endmodule