题解 | #含有无关项的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match );

reg [8:0] shift;

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        shift <= 9'b0;
    else
        shift <= {shift,a};
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        match <= 1'b0;
    else if(shift[8:6]==3'b011 && shift[2:0]==3'b110)
        match <= 1'b1;
    else
        match <= 1'b0;
end

endmodule