题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns

module seq_circuit( input C , input clk , input rst_n,

output wire Y
);

reg [1:0] curr_state;
reg [1:0] next_state;

always@(posedge clk or negedge rst_n) begin
    if(!rst_n)
        curr_state <= 2'b00;
    else
        curr_state <= next_state;
end

always @(*) begin
    next_state = 2'b00;
    case(curr_state)
        2'b00 : begin
            if(C == 1'b0) begin
                next_state = 2'b00;
            end else begin
                next_state = 2'b01;
            end
        end
        2'b01 : begin
            if(C == 1'b0) begin
                next_state = 2'b11;
            end else begin
                next_state = 2'b01;
            end
        end
        2'b10 : begin
            if(C == 1'b0) begin
                next_state = 2'b00;
            end else begin
                next_state = 2'b10;
            end
        end
        2'b11 : begin
            if(C == 1'b0) begin
                next_state = 2'b11;
            end else begin
                next_state = 2'b10;
            end
        end
        default : next_state = 2'b00;
    endcase
end

assign Y = (curr_state[1] & curr_state[0]) | (curr_state[1] & C);

endmodule