题解 | #脉冲同步电路#

1. 第一种方法，经典握手。

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);
    //defination
    reg signal_a_ex;
    reg signal_b_r;
    reg signal_b_rr;
    reg signal_b_rrr;
    reg signal_a_r;
    reg signal_a_rr;
    reg signal_a_rrr;
    wire signal_a_pos;
    
    //output
    always@(posedge clk_fast or negedge rst_n)begin
        if(!rst_n) signal_a_ex <= 'd0;
        else if(data_in) signal_a_ex <= 1'b1;
        else if(signal_a_pos) signal_a_ex <= 1'b0;
    end
    
    always@(posedge clk_slow or negedge rst_n)begin
        if(!rst_n) {signal_b_rrr, signal_b_rr, signal_b_r} <= 'd0;
        else {signal_b_rrr, signal_b_rr, signal_b_r} <= {signal_b_rr, signal_b_r, signal_a_ex}; 
    end

    assign dataout = ~signal_b_rrr && signal_b_rr;
    
    always@(posedge clk_fast or negedge rst_n)begin
        if(!rst_n) {signal_a_rrr, signal_a_rr, signal_a_r} <= 'd0;
        else {signal_a_rrr, signal_a_rr, signal_a_r} <= {signal_a_rr, signal_a_r, signal_b_rr}; 
    end
    
    assign signal_a_pos = ~signal_a_rrr && signal_a_rr;
endmodule

2. 第二种方法是新学的，扩展信号检测到data_in就翻转，慢时钟域直接进行边沿检测就行了，第一种方法是默认上升沿检测的，面积和功耗相比之下还是太大了。

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);
    //defination
    reg signal_a_ex;
    reg signal_b_r;
    reg signal_b_rr;
    reg signal_b_rrr;
    
    //output
    always@(posedge clk_fast or negedge rst_n)begin
        if(!rst_n) signal_a_ex <= 'd0;
        else if(data_in) signal_a_ex <= ~signal_a_ex;
    end
    
    always@(posedge clk_slow or negedge rst_n)begin
        if(!rst_n) {signal_b_rrr, signal_b_rr, signal_b_r} <= 'd0;
        else {signal_b_rrr, signal_b_rr, signal_b_r} <= {signal_b_rr, signal_b_r, signal_a_ex}; 
    end

    assign dataout = signal_b_rrr ^ signal_b_rr;
endmodule