题解 | #脉冲同步电路#

`timescale 1ns/1ns //yysyrst_n一般是高信号复位，但是这个是低信号复位，但是不影响。 module pulse_detect( input clk_fast , input clk_slow ,
input rst_n , input data_in ,

output              dataout

); reg reg1_clk1; reg reg1_clk2; reg reg2_clk2; reg reg3_clk2; always@(posedge clk_fast or negedge rst_n) begin if(!rst_n) begin reg1_clk1<=1'b0; end else if(data_in==1'b1) begin reg1_clk1<=~reg1_clk1; end else begin reg1_clk1<=reg1_clk1; end end always@(posedge clk_slow or negedge rst_n) begin if(!rst_n) begin reg1_clk2 <=1'b0; reg2_clk2 <=1'b0; reg3_clk2 <=1'b0; end else begin reg1_clk2<=reg1_clk1; reg2_clk2<=reg1_clk2; reg3_clk2<=reg2_clk2; end end assign dataout=reg2_clk2^reg3_clk2; endmodule