题解 | #四选一多路器#

`timescale 1ns/1ns module mux4_1( input [1:0]d1,d2,d3,d0, input [1:0]sel, output[1:0]mux_out ); //**code//

reg [1:0] temp;
always@(*) begin
    case(sel)
        2'b00: temp =d3;
        2'b01: temp =d2;
        2'b10: temp =d1;
        2'b11: temp =d0;
        default :temp=0;
    endcase
end
assign mux_out=temp;

//**code// endmodule