`timescale 1ns/1ns module odo_div_or ( input wire rst , input wire clk_in, output wire clk_out7 ); //*************code***********// reg [2:0] cnt; wire tff1_en; wire tff2_en; reg div1; reg div2; assign tff1_en = (cnt==6)?1'b1:1'b0;//N拉高上升沿触发电路 assign tff2_en = (cnt=...
